Latch circuit tolerant of undefined control signals

ABSTRACT

A master slave latch circuit wherein the output impedances of the input and latching gates in both the master and slave sections are adjusted to prevent the two input gates from turning on simultaneously.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a latch circuit used for a semiconductorintegrated circuit device or the like.

2. Background Art

FIG. 12 shows a general master/slave latch circuit. In FIG. 12 is shownan input A to a master latch circuit M. An input B to a slave latchcircuit S is the output of the master latch circuit M. Also shown are anoutput C of the slave latch circuit S and a control signal φ. A masterinput gate G₅ and a slave latching gate G₈ have enable state and disablestates controlled by a control signal φ and have respective outputs 0₅and 0₈. A master latching gate G₆ and a slave input gate G₇ have theirenable states and disable states controlled by a control signal -φ andhave respective outputs O₆ and O₇. The control signal -φ is thecomplement of the control signal φ. The master latch circuit M containsa buffer B₃ and the slave latch circuit S contains a buffer B₄.

FIG. 13 is a table indicating the states of the gates G₅ through G₈ andof the latch circuit outputs B and C with the states of the controlsignal φ.

The operation of the conventional master/slave latch circuit will bedescribed.

When the master input gate G₅ and the slave latching gate G₈ are enabledby the control signal φ, the gates G₆ and G₇ are disabled. As a result,the signal of the input A is applied to the output 0₅ of the gate G₅.Simultaneously, in the slave latch circuit S the signal of the output Cexisting before the change of the control signal φ is latched by thegate G₈ and the buffer B₄. When the control signal φ is inverted, thegates G₅ and G₈ are disabled while the gates G₆ and G₇ are placed in anenabled state. Under this condition, in the master latch circuit M, thesignal of the output B existing before the control signal φ is invertedis latched by the gate G₆ and the buffer B₃. At the same time, thesignal of the output B latched by the master latch circuit M istransmitted through the gate G₇ in the slave latch circuit S and thustransmitted to the output C.

The conventional master/slave latch circuit suffers from a difficultythat, when the potential of the control signal φ becomes unstablebetween the "H (high)" potential and the "L (low)" potential (forinstance the potential of the control signal φ changes slowly from "L"to "H"), the signal of the input A read into the master latch circuit Mis directly transmitted to the output C of the slave latch circuit S.The signal provided at the output B (described later) is determined bywhich one of the outputs of the master input gate G₅ and the slavelatching gate G₈ has the smaller output impedance. Similarly, the signalprovided at the output C is determined by which one of the outputs ofthe master latching gate G₆ and the slave input gate G₇ has the smalleroutput impedance. These output impedances are determined depending uponperformances of transistors used therein.

On the other hand, in the conventional master/slave latch circuit, inorder to decrease the delay time of signal transmission from the input Ato the output B and from the input B to the output C, the input gate G₅in the master latch circuit and the input gate G₇ in the slave latchcircuit are made large in transistor size. Also, in order to reduce thechip size of the semiconductor integrated circuit device or the like themaster latching gate G₆ and the slave latching gate G₈ are made small intransistor size. Accordingly, in the above-described case, when thepotential of the control signal φ is φ₃ (O<φ₃ <φ_(O)), the outputimpedance Z₅ equal to the output impedance Z₆ of the master latchinggate G₆. Furthermore, when the potential of the control signal φ is φ₄(φ₀ <φ₄ <V_(cc)), the output impedence Z₇ F of the slave input gate G₇becomes equal to the output impedance Z₈ of the slave latching gate G₈.Therefore, when φ₃ <φ<φ₄, the output impedance Z₅ of the master inputgate G₅ is lower than the output impedance Z₆ of the master latchinggate G₆, and the output impedance Z₇ of the slave input gate G₇ is lowerthan the output impedance Z₈ of the slave latching gate G₈. As a resultof this, at the output B the output O₅ of the master input gate G₅ isprovided as a "master" output while the output O₆ of the master latchinggate G₆ is provided as a "slave" output. Also, at the output C theoutput O₇ of the gate slave input G₇ is provided as a "master" outputwhile the output O₈ of the slave latching gate G₈ is provided as a"slave" output. That is, both of the outputs O₅ and O₇ from the inputgates G₅ and G₇ are provided as "master" outputs, and the signal of theinput A read into the master latch circuit M is transmitted directly tothe slave latch circuit output C with the result that the function ofthe master/slave latch circuit is not correctly performed. That is, themaster/slave latch circuit operates erroneously.

SUMMARY OF THE INVENTION

Accordingly, an object of this invention is to eliminate theabove-described difficulties accompanying a conventional master/slavelatch circuit.

More specifically, an object of the invention is to provide amaster/slave latch circuit in which its original master/slave latchfunction is correctly performed and the erroneous operation isprevented.

A master/slave latch circuit according to the invention is so designedthat, irrespective of the magnitude of voltage of a gate control signal,the output of a reading gate in the master latch circuit and the outputof a reading gate in the slave latch circuit are not provided as"master" outputs simultaneously.

In the master/slave latch of the invention, there is provided a meansfor preventing, irrespective of the value of voltage of the gate controlsignal, the simultaneous output of the input gate in the master latchcircuit and the output of the input gate in the slave latch circuit.Thus, the outputting of the input signal of the master latch circuitdirectly from the slave latch circuit is prevented.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a master/slave latch circuit whichis a first embodiment of this invention.

FIG. 2 is a diagram indicating the states of various gates with thestates of a control signal φ.

FIG. 3 is a diagram showing equivalent circuits of the master latchcircuit and the slave latch circuit with φ=-φ=φ_(O).

FIGS. 4, 5, 7, 8, 10 and 11 are circuit diagrams showing master/slavelatch circuits which are other embodiments of the invention.

FIG. 6 is a diagram showing examples of clocked gates employed in thecircuits of FIGS. 7 and 8.

FIG. 9 is a diagram showing examples of transmission gates used in thecircuits of FIGS. 10 and 11.

FIG. 12 is a circuit diagram showing a conventional ordinarymaster/slave latch circuit.

FIG. 13 is a diagram indicating the states of various gates with thestates of a control signal φ.

In these figures, like parts are designated by like reference numeralsor characters.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A first embodiment of this invention will be described with reference toFIG. 1. The outward form of this circuit is the same as that of FIG. 12,although the elements have been renumbered. Most importantly, the outputimpedances of the gates are restricted.

Moreover, the associated logic table is different. FIG. 2 indicates thestates of outputs O₁ through O₄ of gates G₁ through G₄ and the latchcircuit outputs B and C as a function of the voltages of the controlsignal φ. FIG. 3 shows equivalent circuits of the master and the slavelatch circuits in the case when φ=-φ=φ_(O), showing the variation inpotential of the output B. In FIG. 3, reference characters Z₁ through Z₄designate respectively the output impedances of the master input gateG₁, the master latching gate G₂, the slave input gate G₃ and the slavelatching gate G₄. It is required that Z₁ is equal to or greater than Z₂and Z₃ is greater than Z₄ and these output impedances are selected fromthe range of 100 ohms to 1,000 ohms so as to meet the characteristics oftransistors used therein. B₁ and B₂ respectively represent the buffersin the master latch circuit and the slave latch circuit.

The enabled and disabled states of the gates G₁ and G₄ are controlled bythe control signal φ while the enabled and disabled states of the gatesG₂ and G₃ are controlled by the complemented control signal -φ. When thegates G₁ and G₄ are in the enabled state and the gate G₂ and G₃ are inthe disabled state, in the master latch circuit the signal of the inputA is transmitted to the output O₁ of the master input gate G₁ while inthe slave latch circuit the signal of the output C provided before thechange of the control signal φ is latched by the slave latching gate G₄and the buffer B₂. Upon the inversion of the control signal φ, the gatesG₁ and G₄ are disabled while the gates G₂ and G₃ are enabled. In thisoperation, in the master latch circuit, the signal of the output Bprovided before inversion of the control signal φ is latched by themaster latching gate G₂ and the buffer B₁, while in the slave latchcircuit the signal of the output B thus latched is read by the slaveinput gate G₃ and transmitted to the output C.

In the above-described embodiment, as shown in FIG. 3, when φ=-φ=φ_(O),in the master latch circuit, the output impedance Z₂ of the latchinggate G₂ is less than the output impedance Z₁ of the input gate G₁.Therefore, at the master output B, the potential of the output O₂ of themaster latching gate G₂ is provided as a "master" potential while thepotential of the output O₁ of the master input gate G₁ is provided as a"slave" potential (cf. the parts (a) and (b) of FIG. 3). In the slavelatch circuit, the output impedance Z₄ of the latching gate G₄ is lessthan the output impedance Z₃ of the input gate G₃. Therefore, at theslave output C, the potential of the output O₄ of the slave latchinggate G₄ is provided as a "master" potential while the potential of theoutput O₃ of the slave input gate G₃ is provided as a "slave" potential(cf. parts (c) and (d) of FIG. 3).

Accordingly, in the above-described embodiment, as shown in FIG. 2, whenthe potential of the control signal φ is φ₁ (O<φ₁ <φ_(O)), the outputimpedance Z₃ of the slave input gate G₃ becomes equal to the outputimpedance Z₄ of the slave latching gate G₄. Also, when the potential ofthe control signal φ is φ₂ (φ_(O) <φ₂ <V_(cc)), the output impedance Z₁of the master input gate G₁ becomes equal to the output impedance Z₂ ofthe master input gate G₂. Therefore, at the output B, when 0≦φ<φ₂, theoutput O₂ of the master latching gate G₂ is provided as a "master"output while the output O₁ of the gate G₁ is provided as a "slave"output. Also, when φ₂ <φ≦V_(cc), the output O₁ of the master input gateG₁ is provided as a "master" output while the output O₂ of the masterlatching gate G₂ is provided as a "slave" output. And at the output C,when 0≦φ<φ₁, the output O₃ of the slave input gate G₃ is provided as a"master" output while the output O₄ of the slave latching gate G₄ isprovided as a "slave" output. Also, when φ₁ <φ≦V_(cc) the output O₄ ofthe slave latching gate G₄ is provided as a "master" output while theoutput O₃ of the slave input gate G₃ is provided as a "slave" output.Therefore, there is no case in which both of the outputs O₁ and O₃ areprovided as "master" outputs. That is, the difficulty that the signal ofthe input A read by the master latch circuit is transmitted directly tothe slave latch circuit output C will never occur. Thus, the abovedescribed master/slave latch circuit will never operate erroneously.

In the above-described embodiment, the buffers B₁ and B₂ are employed.However, in the case where the output of the gates G₁ through G₄ aresufficiently large, a circuit as shown in FIG. 4 in which the buffers B₁and B₂ are not employed may be used with the same effect as theabove-described embodiment.

In the above-described first embodiment, the output B of the masterlatch circuit is the connecting point of the output O₁ of the masterinput gate G₁ and the output O₂ of the master latching gate G₂. Also,the output C of the slave latch circuit S is the connecting point of theoutput O₃ of the slave input gate G₃ and the output O₄ of the slavelatching gate G₄. However, the circuit may be so modified that, as shownin FIG. 5, the input of the master latching gate G₂ is the output B ofthe master latch circuit M, and the input of the slave latching gate G₄is the output C of the slave latch circuit S.

The first embodiment has been described with reference to the ordinarymaster/slave latch circuit. However, it may be modified as follows. Thegates are replaced by clocked gates as shown in FIGS. 6(a) and 6(b) toform a circuit as shown in FIGS. 7 or 8, and the output impedance Z₁through Z₄ of the clocked gates G₁ through G₄ are determined similarlyas in the case of the above-described embodiment. The modification canprovide the same effect as the above-described embodiment.

Furthermore, transmission gates as shown in the FIGS. 9(a) and 9(b) maybe employed to form a circuit as shown in FIGS. 10 or 11, and the outputimpedance Z₁ through Z₄ of the transmission gates G₁ through G₄ aredetermined similarly as in the case of the above-described embodiment.This modification also can provide the same effect as theabove-described embodiment.

In FIGS. 6 and 9, reference characters P₁ through P₆ designate P-channelMOS transistors, and N₁ through N₆ N-channel MOS transistors.

As is apparent from the above description, the master/slave latchcircuit according to the invention is so designed that, when the voltageof the control signal φ or -φ changes slowly in the range of 0 V toV_(cc), the output of the reading gate in the master latch circuit andthe output of the reading gate in the slave latch circuit may not beprovided as "master" outputs simultaneously. Therefore, the master/slavelatch circuit of the invention is free from the erroneous operation thatthe signal of the input A is transmitted through the output B of themaster latch circuit directly to the slave latch circuit output C.

We claim:
 1. A master/slave latch circuit, comprising:a master latchcircuit comprising a first reading gate and a first latching gate, saidfirst reading gate receiving an input signal on an input thereof andhaving an output connected to a common connection point of said masterlatch circuit, said first latching gate having an output connected tosaid common connecting point of said master latch circuit, a controlsignal and an inverted control signal being applied to control inputs ofsaid first reading gate and said first latching gate, respectively, andsaid first reading gate having an output impedance equal to or largerthan an output impedance of said first latching gate; and a slave latchcircuit comprising a second reading gate and a second latching gate, aninput of said second reading gate being connected to said commonconnection point of said master latch circuit and an output of saidsecond reading gate being connected to a common connection point of saidslave latch circuit, said second latching gate having an outputconnected to said common connecting point of said slave latch circuit,said inverted control signal and said control signal being applied tocontrol inputs of said second reading gate and said second latchinggate, respectively, and said second reading gate having an outputimpedance greater than an output impedance of said second latching gate.2. A latch circuit as recited in claim 1, wherein said first and secondreading and latching gates are all clocked gates.
 3. A latch circuit asrecited in claim 1, wherein said first and second reading and latchinggates are all transmission gates.